From EP 1 434 274 A2 there is known a buried gate-type semiconductor device in which the interval between adjacent buried gate is minimized so as to improve channel concentration thereby realizing low ON-resistance. Voltage-resistance reduction due to the concentration of electrical fields in the vicinity of the bottom of the gates is prevented and good OFF characteristics are achieved at the same time by means of P+ body regions deeper than the bottom portion of the buried gates. A plurality of gate electrodes each having a rectangular section are disposed in the plane of a substrate. The interval between the long sides of the gate electrodes is made shorter than the interval between the short sides thereof. Further, a belt-like contact opening is provided between the short sides of the gate electrode, so that P+ body regions and N+ source region are in contact with a source electrode.
From U.S. Pat. No. 6,194,741 B1 there is known a MOS gated trench type power semiconductor device which is formed in 4H silicon carbide with the low resistivity direction of the silicon carbide being the direction of current flow in the device drift region. A P type diffusion at the bottom of the U shaped grooves in N-silicon carbide helps to prevent breakdown of the gate oxide at the trench bottom edges. The gate oxide may be shaped to increase its thickness at the bottom edges and has a trapezoidal or spherical curvature.
From US 2011/00818004 A1 there is known there is known a silicon carbide trench MOSFET possessing both narrow regions where the p body concentration is low, and wide regions where the p body concentration is high. The source electrode is in direct contact with a stripe-shaped p+ type region between two neighboring rows of trench MOSFET cells.
Most of the commercially available power field effect transistors based on silicon carbide (SiC) are implemented with a planar design, where a channel is formed on a surface of a wafer, such as in a vertical double diffused metal oxide semiconductor field effect transistor (VDMOS). However, current densities in these devices are difficult to increase since the p-type implantations in an n-channel VDMOS form the gates of a parasitic junction field effect transistor (JFET) that tend to reduce the width of the current flow. Accordingly, the on-state resistance is relatively high in such known device. The power MOSFETs have a parasitic bipolar junction transistor (BJT) as an integral part of its structure. The body region serves as the base, the source as the emitter and the drain as the collector of the parasitic BJT. To keep this parasitic BJT in an off-state at all times by keeping the potential of the base as close to the emitter potential as possible the body and the source of the MOSFET is shortened. Otherwise, the potential at the base may turn on the parasitic BJT and lead the device into the “latchup” condition, which would destroy the device. Therefore, in the known n-channel VDMOS the p-well forming the body region is connected to the source metallization, so that the parasitic BJT is shorted. In order that the short has little resistance, the doping is increased at this spot by an additional p+-implantation, followed by a diffusion step to form highly doped p-type body contact regions.
Trench metal oxide semiconductor field effect transistors (MOSFETs) with a U-shaped channel enable the achievement of low on-state resistance because of lack of the parasitic JFET. Additionally, for SiC, the trench MOSFET architecture permits optimization of carrier mobility by designing the channel with respect to different crystallographic planes. A SiC trench MOSFET is known for example from US 2014/0034969 A1. As in an n-channel VDMOS, also in an n-channel trench MOSFET the p-type body regions include the highly doped p-type contact regions which are connected to the source metallization to shorten the parasitic BJT, which is present also in the trench MOSFET.
In the Proceedings of the 27th International Symposium on Power Semiconductor Devices & ICs (ISPSD), May 10-14, 2015, Kwoloon Shangri-La, Hong Kong, it is disclosed the so called trench-etched double-diffused SiC MOS (TED MOS) in order to improve both conduction loss and switching loss. It is claimed that the trench side channels of TED MOS can provide both high channel mobility and wide channel width to decrease on-state resistance (RonA). Moreover, TED MOS also achieves low gate-to-drain capacitance Qgd because its gates and trenches are completely covered with a P-body region. Experimental results show that the figure of merit (RonA·Qgd) of the TED MOS can be reduced by 70% compared to that of a conventional DMOS. In fact, the TED MOS design is basically a planar design with extended channel area, where the current flows horizontally. The drawback of such design is the long channel length required, which reduces on-state current, as well as the need for large areas for its cells and the presence of JFET regions, which increase the on-state resistance as discussed above for the known VDMOS.
It is the object of the invention to provide a power semiconductor device with higher on-state current while suppressing short channel effects.
The object of the invention is attained by a power semiconductor device according to claim 1.
The power semiconductor device of the invention is a power field effect transistor device that has a trench with a double gate, where the current flows vertically. Contrary to the known standard trench design of vertical power MOSFETs, the power semiconductor device of the invention creates multi-gate regions to thereby enhance the gate control. This is achieved by a different three-dimensional layout of the device regarding the source layer and the distribution of first ohmic contacts in an area between each pair of adjacent gate strips as defined in claim 1. In the power semiconductor device of the invention the double gate distance, which is the distance between the two lateral surfaces of a body region in a vertical FET cell, can be reduced to achieve improved electrostatic gate control and, therefore, a higher on-state current. The specific layout of the invention allows a better packing, i.e. a higher density of vertical FET cells and, therefore, a higher on-state current. In the invention, the source layer does not extend onto the top surface of each body region, such that the whole top surface of the body region facing away from the substrate layer is in direct contact with the gate insulation layer. This has the advantage that the body region is free of electrons in the off-state.
Further developments of the invention are specified in the dependent claims.
In an exemplary embodiment, a body contact region is arranged between each pair of adjacent gate strips, each body contact region being a semiconductor region of the second conductivity type having a doping level higher than that of the body layer and penetrating through the source layer to extend to and contact the body layer, wherein the source electrode is arranged on the body contact region to form a second ohmic contact to the body contact between each pair of adjacent gate strips. In this exemplary embodiment a parasitic bipolar junction transistor (BJT) is efficiently shortened.
In an exemplary embodiment, a distance between the two lateral surfaces of each body region is 1 μm or less, exemplarily 500 nm or less, more exemplarily 100 nm or less and more exemplarily 20 nm or less. With reduced distance between the lateral surfaces of each body region, i.e. with reduced double gate distance electrostatic gate control can be enhanced and accordingly a higher on-state current can be achieved. The effect becomes significant at a distance between the lateral surfaces of each body region (double gate distance) of about 1 μm. In addition, short-channel effects can be significantly reduced at the same time due to enhanced electrostatic gate control in forward direction.
In an exemplary embodiment, a first thickness of a first portion of the gate insulation layer separating the lateral surface of each body region from the gate layer is in a range between 10 nm and 100 nm.
In an exemplary embodiment, a second thickness of a second portion of the gate insulation layer separating the top surface of each body region from the gate layer is in a range between 10 nm and 500 nm.
In an exemplary embodiment, a ratio between the first thickness and the second thickness is less than 0.5. A design where the second thickness is relatively higher than the first thickness has the advantage that the switching speed can be increased.
In an exemplary embodiment, the distance between each pair of body regions neighboring in the first direction is 1 μm or less, exemplarily 500 nm or less, more exemplarily 100 nm or less and more exemplarily 20 nm or less.
In an exemplary embodiment, the source layer extends onto the top surface of each body region.
In an exemplary embodiment, the whole top surface of each body region is separated from the gate insulation layer in a direction vertical to the main surface of the substrate layer.
In an exemplary embodiment, a semiconductor well of the second conductivity type is formed on a bottom side of each first gate region facing towards the substrate layer, the semiconductor well region being separated and electrically insulated from the first gate region by the gate insulation layer. The semiconductor well can electrostatically protect the gate of the device.
In an exemplary embodiment, at least the substrate layer, the body layer and the source layer are formed of silicon carbide.
In an exemplary embodiment, each body contact region between two adjacent gate strips is a continuous strip-shaped region. Throughout the description a strip-shaped region is a long, narrow region having a significantly larger dimension along its longitudinal axis than along any other direction perpendicular to the longitudinal axis. A dimension is considered to be significantly lager if it is at least three times larger. With such design the parasitic bipolar transistor formed by the body region (base of the parasitic BJT), the source (emitter of the parasitic BJT) and the drain (collector of the parasitic BJT) can be kept in an off-state most reliably.
In an exemplary embodiment, at least the body regions of each row of vertical field effect transistors are connected with each other by a continuous portion of the body layer.
In an exemplary embodiment, the lateral surfaces of each body region are parallel to each other. With such design a good homogeneous electrostatic gate control throughout the body region can be ensured.
In an exemplary embodiment, the substrate layer comprises a drift layer and a drain layer, the drain layer having a higher doping level than the drift layer and being separated from the body layer by the drift layer.
The reference signs used in the figures and their meanings are summarized in the list of reference signs. Generally, similar elements have the same reference signs throughout the specification. The described embodiments are meant as examples and shall not limit the scope of the invention. The comparative example described with FIGS. 1 to 4 does as such not form part of the claimed invention but serves for a better understanding thereof.